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MetaVia Unstop

Posted today

ASIC Engineer Intern, Design Verification

Pay

Stipend (undisclosed)

Location

Bangalore, India

On site

Type

Internship

Apply by

11 Nov

13 days left

Skills this role screens for

SystemverilogComputer architectureVerification and validation (v&v)C programming languageDebugging

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About the role

Meta is hiring for the role of ASIC Engineer Intern, Design Verification!

The work

Responsibilities of the Intern

  • Develop tests, checkers and coverage to help verify designs.
  • Develop understanding of the architecture and microarchitecture of designs.
  • SystemVerilog/UVM/C code to generate test content.
  • Develop scripts to automate various processes.
  • Debug test failures, work with design, verification and modeling teams to fix and verify the fixes.
  • Help improve verification processes and contribute to methodology.

Who they want

Requirements

  • Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
  • Knowledge of Computer Architecture and Logic Design fundamentals
  • Experience thinking critically and creatively on how to verify designs, solve problems
  • Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
  • Intent to return to degree-program after the completion of the internship

Where this listing comes from

From a public listing board (Unstop).

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